Multi-rate digital filter for audio sample-rate conversion

ABSTRACT

In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates to audio sample-rate conversion systems,and more particularly relates to multistage sample-rate conversionfilters.

BACKGROUND OF THE INVENTION

[0002] For both historical and technical reasons, there have existed anumber of industrial standards on audio digital signal sample rates. Thewell known examples are the 44.1 kHz sample rate for consumer CD playersand 48 kHz for professional digital audio. This, in turn, has given riseto sample-rate conversion (“SRC”) systems for converting a stream ofdigital data at one sample rate to a stream of digital data at adifferent sample rate. However, the cost of existing SRC systems ishigh. This imposes a severe constraint in designing more affordabledigital audio products that apply to various source signals.

[0003] Early implementations of SRC systems were done in a hybriddigital/analog domain. They were relatively simple, since all that isneeded is a digital-to-analog (D/A) converter followed by ananalog-to-digital (A/D) converter. The D/A converter runs at the inputsample rate while the A/D converter is controlled by the output samplerate. If the output sample rate is lower, an analog anti-aliasing filteris provided between them. These three components are expensive andconsume a large amount of power, if designed for minimum signaldegradation.

[0004] Performing sample-rate conversion (SRC) in the digital domain hasbeen a research/development topic for more than a decade. The article byR. E. Crochiere and L. R. Rabiner, “Interpolation and decimation ofdigital signals-A tutorial review,” Proc. IEEE, vol. 69, pp. 300-331,March 1981, is an excellent reference for understanding fundamentalinsights from early research results in this art area. Real-time,all-digital SRC systems are becoming more and more significant becausedigital processing of signals, such as voice, audio and video, appearsto be increasingly dominant over traditional analog methods thanks tohigher signal quality, rich features and the continually lowering costof digital signal processing.

[0005]FIG. 1 shows a typical, all-digital SRC system 10 consisting ofthree basic building blocks: an interpolator (expander) 12, a highquality lowpass digital filter 14, and a decimator 16. The expander 12takes an input stream of samples at one frequency, for example F_(s)_(—) _(in), and digitally produces a stream of digital samples at ahigher rate that is an integer multiple, designated R in this example,of the input rate. Thus, the output of expander 12 is a stream ofdigital samples at a rate of F_(s) _(—) _(out)=RF_(s) _(—) _(in). Thedecimator does the reverse. Thus, the decimator 16 takes an input streamof samples at one frequency, for example X=RF_(s) _(—) _(in), anddigitally produces a stream of digital samples at a lower rate, dividedby an integer division factor, designated S in this example, of theinput rate. This is referred to as decimation, or, alternatively,downsampling. Thus, the output of decimator 16 is a stream of digitalsamples at a rate of X/S=F_(s) _(—) _(out)=(R/S)F_(s) _(—) _(in).

[0006] The reason for performing expansion followed by decimation isthat the input sample rate and the output sample rate may not be asimple integer multiple of one another. The ratio of the interpolationfactor R over the decimation factor S is the SRC ratio R/S where both Rand S are positive integers. For R>S the SRC system is said to beoperated in an SRC-UP mode, whereas an SRC-DOWN mode means R<S.

[0007] R and S may be chosen to have large values in order to achievehigher quality SRC. However, when the values of R and S are high,very-high order digital filters, usually finite impulse response (“FIR”)digital filters, are necessary. Thus, as S and R increase, a greatlyincreasing amount of coefficient memory is required. For example, at asample rate of 48 kHz an equi-ripple prototype FIR filter withtransition bandwidth of Δf=4 kHz, passband ripples=10⁻³ and stopbanderrors=10⁻⁵, has an order of approximately 128. The order of lowpassfilter 14 in FIG. 1 is 128R for an interpolation filter (R is theinterpolation factor up to over 1000).

[0008] It is actually quite difficult or even impossible as a practicalmatter to design an equi-ripple FIR filter with tens of thousands oforders. In fact, the major difficulty encountered in existing audio SRCsystem, implemented either in an application-specific integrated circuit(ASIC) or on a programmable digital signal processor (DSP) such as aTexas Instruments TMS320 series DSP chip, seems to be large memory sizeand high computational complexity. For example, an ASIC described in anarticle by R. Adams and T. Kwan, “A stereo asynchoronous digitalsample-rate converter for digital audio,” IEEE J. Solid-State Circuits,vol. 29, pp. 481-488, April 1994, needs tens of kilobytes of memory tostore just a fraction of the nearly 10 million filter coefficients used.

[0009] Moreover, filter coefficient interpolation, which is performed togenerate thousands of sets of required polyphase filter coefficients inreal time, expends significant computational power which is provided bya hardware multiplier plus an accumulator. A similarly difficultsituation is also encountered when a programmable DSP chip is employed.For example, see the article by S. Park et al., “A novel structure forreal-time digital sample-rate converters with finite precision erroranalysis,” Proc. Int. Conf. on Acoust, Speech and Signal Processing, pp.3613-3616, Toronto, 1991. Several kilobytes of memory are employed inthese SRC systems for filter coefficients alone, in addition to theircomputational complexities falling in the neighborhood of 10 MIPs forone channel of high quality audio.

[0010] Therefore, attempts have been made using window techniques, forexample using a Kaiser window, to design extremely high-order FIRfilters. By using an interpolation technique in calculating requiredcoefficients in real-time, a single-stage SRC filter system, such as thesystem 10 shown in FIG. 1, has become closer to practical, and hardwareimplementation examples have been reported. Examples may be found, e.g.,in U.S. Pat. Nos. 4,780,892, 4,564,918, 4,825,398 and 4,748,578.However, these implementations fall short of the desired efficienciesallowing their utilization in affordable digital audio products forconsumers.

[0011] Other attempts at avoiding the use of high-order filters make useof special functions such as Lagrange polynomials or B-spline functions.See, for example, T. O. Ramstad, “Digital methods for conversion betweenarbitrary sampling frequencies,” IEEE Trans. Acoust, Speech and SignalProcessing, vol. ASSP-32, pp. 577-591, June 1984, for an article on theformer, and S. Cucchi et al., “DSP implementation of arbitrary samplingfrequency conversion for high quality sound application,” Proc. Int.Conf. on Acoust, Speech and Signal Processing, pp. 3609-3612, Toronto,1991, for the latter. These methods, however, all have the drawback ofrequiring a very large number of computations.

[0012] It is known that multistage decimation or interpolation filtersare generally more efficient than single-stage filters, in terms ofcomputational complexity. It appears that the same conclusion also holdson memory requirements of multi-stage filters over single-stageversions. It would therefore be desirable to have a multi-stage schemeemploying a far smaller memory than required in the prior art to storesome of the SRC filter coefficients, and have an accompanyingarrangement for efficiently calculating the rest of the filtercoefficients, in real time.

[0013] Therefore, it is an object of this invention to provide anefficient multistage multi-rate filter. It is also an object of thepresent invention to provide a multistage SRC filter that is moreefficient in both computational and memory requirements than prior artmultistage SRC filter implementations. It is a further object of thepresent invention to provide a multistage SRC that represents a balanceof resource considerations.

SUMMARY OF THE INVENTION

[0014] In accordance with the present invention there is provided amethod for providing a sample-rate conversion (“SRC”) filter on an inputstream of sampled data provided at a first rate, to produce an outputstream of data at a second rate different from the first rate. The inputstream of sampled data is operated on with a first low-orderinterpolation filter routine to produce a first stream of intermediatedata. The first stream of intermediate data is operated on with a firstsimplified interpolation filter routine, having a substantially smallnumber of operations to calculate the coefficients thereof, to produce asecond stream of intermediate data. The second stream of intermediatedata is operated on with a first decimating filter routine to producethe output stream of data.

[0015] Implementations of the present invention can exhibit excellentcharacteristics such as an extremely low memory requirement, simpledesign and implementing procedure and moderate computational complexity.

[0016] Filter performance of the new implementations can easily reach100 dB signal-to-noise-ratio (SNR) level. The simplicity inherent in thepresent invention allows hardware implementation, by using either anASIC or a programmable DSP chip, to be easier and more straightforwardthan heretofore.

[0017] These and other features of the invention will be apparent tothose skilled in the art from the following detailed description of theinvention, taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a block diagram showing a typical, all-digital SRCsystem;

[0019]FIG. 2 is a block diagram showing a preferred embodiment of thepresent invention;

[0020]FIG. 3 is a graph showing the frequency response of a stage-3filter, with r=3;

[0021]FIG. 4 is a more detailed diagram of a preferred embodiment of thepresent invention;

[0022]FIG. 5 is a flow chart showing the general method for indexingused in the preferred embodiment of the present invention;

[0023]FIG. 6 is a block diagram of a simplified model for explaining theindexing used in the preferred embodiment of the present invention;

[0024]FIG. 7 is a block diagram of a more detailed model for explainingthe indexing used in the preferred embodiment of the present invention;

[0025]FIG. 8 is a schematic diagram depicting a data output stream as aseries of vectors; and

[0026]FIG. 9 is a diagram of an SRC filter that utilizes a Σ-•Δmodulator.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0027] The four stage SRC filter structure 20 depicted in FIG. 2 is ablock diagram of a preferred embodiment of the present invention. Itrepresents an excellent balance between easy design procedure, reducedmemory/computation needs, and simple system control flow. The SRC filterstructure 20 comprises a stage-1 expander/filter 22, a stage-2expander/filter 24, a stage-3 expander/filter 26 and a stage-4 decimator28. The stage-4 decimator 28 can be a simple factor of S prior artdecimator, and so the discussion that follows focuses on how best toapply the principles of the present invention to design efficientlyembodiments of the first three filters in stages 1, 2 and 3, and how todesign them for optimum performance. As an initial matter in thatregard, only FIR filters are utilized in the embodiments disclosedherein, because they offer linear phase responses and efficientpolyphase implementations in multirate processing. However, infiniteimpulse response (“IIR”) digital filters may be used, if desired.

[0028] Further, while the embodiment of the present invention disclosedin detail herein utilizes three expander/filter stages, this is onlypreferred, but not required. Two of such stages, or, alternatively,greater than three such stages may be used in the application of theprinciples of the present invention, and still remain within the scopeof the present invention as defined by the appended claims.

[0029] Now, returning to the preferred embodiment, the stage-1expander/filter 22 performs an interpolation of factor R₁. The value ofR₁ is relatively small so that the transition bandwidth of the stage-1expander/filter 22 is still reasonably large. The reason for this isthat a large value of R₁, causing a high output sample rate at thestage-1 expander/filter 22, can lead to an extremely narrow transitionband that, in turn, proportionally results in a very high-order forstage-1 filters, which is undesirable. It is desirable to maintain theorder of the stage-1 filter between 100 and 800.

[0030] With a small vale of R₁, the output sample rate in the stage 2expander/filter 24 is relatively high. However, even though the outputsample rate is significantly higher in the stage-2 expander/filter 24than in the previous stage, the transition band of the stage-2expander/filter 24 can be more relaxed than that of stage 1 since alarge number of the image bands have been already removed by the stage-1expander/filter 22, preferably at least half of the image bands. Theselection of R₂ is not arbitrary, however, because it is desirable tosimplify the stage-3 expander/filter 26 given that it is running at arather high sample rate, R₁R₂F_(s) _(—) _(in). Thus, the choice of R₂depends on how the stage-3 expander/filter 26 is designed.

[0031] The design aspects of the stage-3 expander/filter 26 occupy asignificant role in the design of the preferred embodiment of thepresent invention. A key aspect is that the stage-3 expander/filter 26is a relatively simple filter. Simple filters have trivial filtercoefficients, and the simplest non-zero filter coefficients are simplyones. Further, the stage-3 expander/filter 26 is cascaded. As a generaldesign matter, it should be appreciated that a trivial-coefficient-basedfilter can perform acceptably if it is cascaded, even if only two times.

[0032] The underlying principles for the stage-3 expander/filter 26 arenow described. Let the stage-3 expander/filter 26 be a cascade of rall-one-coefficients filters that are described by: $\begin{matrix}{{H_{3}(z)} = ( {\sum\limits_{k = 0}^{R_{3} - 1}z^{- k}} )^{r}} & {{Eq}.\quad (1)}\end{matrix}$

[0033] Notice that, for simplicity, a normalization factor has beenomitted in Equation (1). Using the filter described by Equation (1) instage 3 substantially removes a significant hurdle that has existedheretofore in designing SRC systems: huge storage requirements forfilter coefficients. As is shown below, the coefficients of H₃(z) can beevaluated based on very simple equations when r is small, say r=2 or 3.The magnitude response of H₃(z) is easily evaluated as: $\begin{matrix}{{{H_{3}( ^{j\quad \omega} )}} = ( \frac{\sin ( {\omega \quad {R_{3}/2}} )}{\sin ( {\omega/2} )} )^{r}} & {{Eq}.\quad (2)}\end{matrix}$

[0034] The function of H₃(z) is to eliminate the image bands introducedby padding (i.e., inserting) zero-value samples between input samples ofstage 3. Furthermore, the monotonic property of H₃(z) between DC and thefrequency ω₀=2π/R₃, at which the filter frequency response reaches itsfirst null value, allows the evaluation of Equation (2) at just twodigital frequency points to determine the performance of the filter. Thefirst point is${\omega_{1} = {2\quad \pi \frac{f_{p}}{{RF}_{s\_ in}}}},$

[0035] where f_(p) denotes maximum frequency of base band signals, andR=R₁R₂R₃ is the interpolation factor of the whole SRC system. At ω₁:$\begin{matrix}{{{H_{3}( ^{j\quad \omega_{1}} )}} = ( \frac{\sin ( \frac{\pi \quad f_{p}}{R_{1}R_{2}F_{s\_ in}} )}{\sin ( \frac{\pi \quad f_{p}}{{RF}_{s\_ in}} )} )^{r}} & {{Eq}.\quad (3)}\end{matrix}$

[0036] This expression gives the maximum droop in the passband of thestage-3 expander/filter 26. Thus ω₂=ω₀−π/R represents the edge frequencyof the first stopband of the stage-3 filter, and the correspondingfrequency response at ω₂ is: $\begin{matrix}{{{H_{3}( ^{j\quad \omega_{2}} )}} = ( \frac{\sin ( \frac{\pi ( {{2R} - R_{3}} )}{2R} )}{\sin ( \frac{\pi ( {{2R} - R_{3}} )}{2{RR}_{3}} )} )^{r}} & {{Eq}.\quad (4)}\end{matrix}$

[0037] Note the following useful information that is evident from theabove expression:

[0038] Increasing the value of R₁R₂ can greatly improve the filterperformance of stage 3 in both passband and stopband. In other words,the first image band is located further away from base band as R₁R₂increases.

[0039] For large values of R₃, which indeed is the case in many SRCapplications, the frequency responses at •ω₁ and •ω₂ asymptoticallybecome independent of R₃.

[0040] To quantitatively examine the filter performance of stage 3 atboth ω₁ and ω₂ several useful cases are evaluated and shown in Table 1with these parameters: R₃=256(2⁸), f_(p)=20 kHz and F_(s) _(—) _(in)=48kHz. TABLE 1 Stage-3 Filter Performance R₁ R₂ H(e^(j) ^(ω) ¹) (dB)H(e^(j) ^(ω) ²) (dB) 2 4 −0.087r −23.6r 2 8 −0.022r −29.8r 2 16 −0.006r−36.0r 2 32 −0.001r −42.1r 2 64 −0.0003r −48.1r 2 128 −0.0001r −54.2r

[0041] A value of r=3 is an optimally balanced selection, and isconsidered preferred. It will be clear from an inspection of Table 1that a value of r=1 does not provide nearly adequate filter performancein most applications, although the filter coefficients are indeedtrivial.

[0042] With r=2, the coefficients of H₃(z) still remain quite simple:

h ₃(n)=n 1≦n≧R ₃  Eq. (5)

[0043] Notice that the other half (R₃·−1) of the filter coefficients(R₃+1≦n≧2R₃·−1) can be obtained from symmetry. Although this filterprovides good filter performance, over 100 dB stopband rejection fordigital processing of audio signals is often desired. This requires thevalue of R₁R₂ to be at least 256. It will be recalled that it ispreferable to use R₁=2 for the reason previously described. If R₁ isselected to be 2, then to maintain the value of R₁R₂ as at least 256, R₂must be 128 or even larger. Therefore, the sample rate at the output ofthe stage-2 expander/filter 24 reaches a minimum of 256F_(s) _(—) _(in).That is over 10 MHz when F_(s) _(—) _(in)=44.1 kHz or higher. Also, forR₂=128, the order of the stage-2 expander/filter 24 may well increase toover a thousand in order to retain high filter performance. An order ofone thousand means large amounts of memory are required, which isundesirable. It is desirable to maintain the order of the stage-2 filterbetween 100 and 1200.

[0044] With r=3, a high-quality filter is easily achieved even thoughR₁R₂ has a moderate value. FIG. 3 is a chart in which the horizontalaxis represents frequency in Hertz and the vertical axis representsmagnitude of response in dB, showing such a filter's frequency response30 within a frequency range including the first stopband 32 that rejectsthe first image band. The first stopband 32, or equivalently, imageband, starts at 1512 kHz and ends at 1560 kHz with the first nullsitting at 1536 kHz.

[0045] The filter coefficients when r=3 can be evaluated by thefollowing expression: $\begin{matrix}{{h_{3}(n)} = \{ \begin{matrix}\frac{n( {n + 1} )}{2} & {1 \leq n \geq {R_{3} - 1}} \\{\frac{R_{3}( {R_{3} + 1} )}{2} - {( {R_{3} - n} )( {{2R_{3}} - 1 - n} )}} & {R_{3} \leq n \leq {\frac{3R_{3}}{2} - 1}}\end{matrix} } & {{Eq}.\quad (6)}\end{matrix}$

[0046] Notice that R₃ has been assumed to be an even number, and againonly half of the symmetric coefficients are described in Equation (6).The end summing index in Equation (6) simply changes to (3R₃−1)/2 if anodd integer of R₃ is chosen. The evaluating procedure to obtain thosecoefficients is sufficiently straightforward to allow computation inreal time. Thus, each set of polyphase components of H₃(z) consists ofat most three integers that require a total of only three integermultiplications and several additions/shifts. The largest coefficient ofH₃(z) is given by 3R₃R₃/4=3×2¹⁴ for R₃=2⁸, requiring merely 16-bitprecision, which, in turn, requires only 16-bit registers.

[0047] Given r=3, R₂ can be chosen as 8 or 16 for audio SRCapplications. In the following design examples R₂=16 and R₃=256. Ifstrict passband performance is required a simple filter can be employedwith several taps to pre-distort the base-band signals such that thedroop in the passband introduced by the stage-3 expander/filter 26 iswell compensated.

[0048] It is well known that filters with fixed coefficients can beimplemented more efficiently than those having programmablecoefficients. This is particularly true when implementing filters inASICs. Therefore, when implementing H₃(z), since the coefficients aredetermined by the value of R₃ and calculated in real time, the designmust be general enough to accommodate every possible set of filtercoefficients that will arise in a particular implementation. In anyevent, it is desirable to maintain R₃ between 100 and 10,000.

[0049] Upon having chosen the value of R₂ the stage-2 expander/filter 24can easily be made with fixed coefficients. Those fixed coefficients canfurther be represented by canonical signed digits (CSD) form to greatlysimplify computations by using add/shift operations rather than normalmultiplications. Even by using a programmable DSP chip, fixedcoefficients are easier to handle than time-varying coefficients.

[0050] In implementing an embodiment of the present invention particularattention should be made in designing the first stage filter. In thisregard, it should be noted that making distinct the considerationsbetween SRC-UP and SRC-DOWN modes has so far been ignored in thediscussion herein. This will now be discussed. The care that should beexercised in designing efficient stage-1 filters that are able to handleboth UP and DOWN modes highlights an important design consideration whenseeking the high efficiency achievable by the inventive SRC designmethodology disclosed herein.

[0051] Some problems are encountered in design when UP modes areinvolved. They are discussed below. The function of the stage-1 filtersimply erases the image band caused by the first interpolator.Therefore, the stage-1 expander/filter 22 can have fixed coefficients.But in DOWN modes, the stage-1 expander/filter 22 must remove highfrequency components of the input signals in addition to cutting theimage band off.

[0052] Two embodiments of the present invention are presented herein forsolving this problem, in the form of two methods. In the first method,several stage-1 filters may be provided, each of which is suitable to aspecific DOWN mode. The selection from those pre-set filters is easilydone by feeding an index that points to a correct initial memory addressof stored filter coefficients. If desired, those pre-computedcoefficient sets can be stored in a host system such as a personalcomputer to save the memory on an ASIC or DSP chip.

[0053] The second method calls for a real-time computing scheme, similarto H₃(z), that generates filter coefficients based on a generic set offilter coefficients and still meets the filter specifications. Note thatthis computing procedure needs to be executed only once when the SRCratio is changed, and stays on until a new SRC ratio is invoked.Nonetheless, the first of these two methods is considered preferred, andthat method is utilized in the following design examples.

[0054] Designing filters that can be employed for converting samplerates between 44.1 and 48 kHz, based on the above design guidelines,will now be considered.

[0055] A. Stage-1 Filters

[0056] Stage-1 filters having an order of 126 provide adequate filterperformance and require acceptable amounts of memory and computationalcomplexities. In the UP mode, i.e., the 44.1·>48 kHz case, a 126th-orderFIR filter can provide over 100 dB stopband rejection and maintain up to20 kHz passband signals. It is also possible to employ a half-band FIRfilter if a somewhat greater number of aliasing errors can be toleratedin the transition band from 20 kHz to 24 kHz. In half-band FIR filtersone of the two polyphase sub-filters is a delay element. Thereforehalf-band FIR filters need nearly 50% lower computations and coefficientmemory in comparison to normal FIR filters with the same filter orders.To further reduce computations, symmetry in filter coefficients can beused. Indeed, by selecting an even-order, half-band FIR filters havepolyphase components with symmetrical coefficients.

[0057] In the DOWN mode, however, a 126th-order FIR filter can onlymaintain a passband of about 18.5 kHz if the 100 dB stopband rejectionrequirement applies.

[0058] Actual filter coefficients for a Stage-1 filter used in a Matlabsimulation of an embodiment of the present invention are found inAppendix A. The designer may wish to select other coefficients toaccommodate specific application constraints and/or performanceobjectives. Optimal quantization of filter coefficients may beconsidered by the designer, as well. All of such variations are wellwithin the purview of those of ordinary skill in this art area.

[0059] B. Stage-2 Filters

[0060] Only the stage-2 expander/filter 24 should have fixedcoefficients that are independent of the SRC mode. To be consistent withthe filter performance in the stage-1 expander/filter 22 configured asdescribed above, a 143rd-order FIR filter should be used. The ordernumber 143 offers an advantage in that every polyphase component has thesame number of coefficients, that is, nine, when R₂=16. Although thepolyphase components may no longer have symmetric coefficients, half ofthe polyphase components have coefficients that are mirror-symmetricwith their counterparts in the other half of the polyphase components.Such a property may be exploited to save coefficient memories.

[0061] Actual filter coefficients for a Stage-2 filter used in a Matlabsimulation of an embodiment of the present invention are found inAppendix B. The designer may wish to select other coefficients toaccommodate specific application constraints and/or performanceobjectives. Optimal quantization of filter coefficients may beconsidered by the designer, as well. All of such variations are wellwithin the purview of those of ordinary skill in this art area.

[0062] In this connection, the designer may wish to consider for stage-2filters a cascade of several half-band FIR filters having half zerofilter coefficients, which results in a need for only half of thecomputations otherwise, as well as half of the memory requirement. Thedesigner should keep in mind, however, that a drawback of using acascade of several half-band FIR filters is the need for a morecomplicated indexing scheme than that described in the followingsections.

[0063] C. Stage-3 Filters

[0064] This filter has already been discussed in detail in the previoussection. Note, however, that it might be preferred to make this filterfully programmably controlled by selecting R₃ in real time. Rememberthat larger values of R₃ require higher dynamic ranges in filteringcomputations.

[0065] Since the impulse response of this filter is very smooth, it ispossible to compress the coefficients. Piecewise linearization may beused, for example. However, since the coefficients are already easilycalculated, and since the filtering operation does not use neighboringcoefficients in the computation of any given output sample, it is notclear that significant savings would result from compression, but theimplementation enhancement is suggested in the interest of fulldisclosure.

[0066] D. Implementation Architecture

[0067] A more detailed diagram of a preferred implementation of the newSRC filter is shown in FIG. 4. The SRC filter 40 includes threeexpander/filter stages 42, 44, 46, and a decimator stage 48. The stage-1expander/filter 42 includes two polyphase sub-filters 50, 52,corresponding to R₁=2, each receiving the input x(n) provided at asample rate of F_(s) _(—) _(in). The outputs of polyphase sub-filters50, 52, are selected at a rate of 2F_(s) _(—) _(in), as shown by switch54, and provided at that rate as the input x₁(n) to the stage-2expander/filter 44.

[0068] The stage-2 expander/filter 44 includes sixteen polyphasesub-filters 60, 62, 64, . . . 66, corresponding to R₂=16, each receivingthe input x₁(n). The outputs of polyphase sub-filters 60, 62, 64, . . .66, are selected sequentially and cyclically at a rate of 32F_(s) _(—)_(in), as shown by switch 68, and provided at that rate as the inputq(n) to the stage-3 expander/filter 46.

[0069] The stage-3 expander/filter 46 includes R₃ polyphase sub-filters70, 72, 74, . . . 76, each receiving the input q(n). The outputs ofpolyphase sub-filters 70, 72, 74, . . . 76, are selected sequentiallyand cyclically at a rate of 32R₃F_(s) _(—) _(in), as shown by switch 78,and provided at that rate as the input to the stage-4 decimator 48. Theoutput of decimator 48 is the output y(n) of the SRC filter 40.

[0070] In practice, the stage-4 factor-S decimating must be merged intothe three previous stages to avoid any redundant computations that arenot related to output samples at a required sample rate. This isaccomplished in the preferred embodiments herein by a novel indexingtechnique, explained below. The resulting memory size for the SRC filtercoefficients is only 136 words, which is more than an order of magnitudereduction in comparison to the prior art SRC systems described in thearticle by R. Adams and T. Kwan, and the article by S. Park et al.,cited above. On the other hand, the number of multiplications is 97 peroutput sample, a moderate quantity for a high quality SRC system.

[0071] An SRC procedure for converting samples provided at a rate of 48kHz to a rate of 44.1 kHz will now be explained in detail, inconjunction with a Matlab listing implementing such procedure. Thisprocedure includes a novel indexing scheme alluded to above. It will berecalled that it was pointed out that major increases in storage andprocessing efficiencies are obtained in the preferred embodiments by wayof such novel indexing scheme. This indexing is best understood byworking backwards from the output sample. FIG. 5 is a flow chart showingthe steps in determining the current output sample. Thus, the first step80 is to determine which stage-3 output sample will be the current SRCoutput sample. The second step 82 is to determine which stage-2 outputsamples will be used to form the appropriate stage-3 output sample. Thethird step 84 is to determine the coefficients of the stage-3 filtersthat will be applied to the stage-2 output samples to form the neededstage-3 output sample, and to compute those coefficients. The fourthstep 86 is to determine the stage-1 output samples needed to form theneeded stage 2 output samples. The fifth step 88 is to determine thestage-2 filter coefficients needed to form the needed stage-2 outputsamples, and then to retrieve those coefficients from storage. The sixthstep 90 is to determine the input samples needed to form the neededstage-1 output samples. The seventh step 92 is to determine the stage-1filter coefficients needed to form the needed stage-1 output samples,and then to retrieve those coefficients from storage. The eighth step 94is to perform the necessary filtering operations for stages 1, 2, then3. The ninth step 96 is to output the sample and return to the firststep 80.

[0072] The process described above generally, in connection with FIG. 5will now be explained in more detail. First, FIG. 6 is a simplifiedblock diagram showing an SRC filter 140, based on the SRC filter 40 ofFIG. 4, for the case where R₃=147, S=5120 (this is for the case of 48kHz to 44.1 kHz conversion). The input sample rate F_(s) _(—) _(in) isreferred to here, and hereinafter in this document, as F_(s), tosimplify notation. Thus, the output of the stage-1 expander/filter 142is provided at a rate of 2F_(s). The output of the stage-2expander/filter 144 is provided at a rate of 32F_(s). The output of thestage-3 expander/filter 146 is provided at a rate of 147*32F_(s).Decimation is performed by selecting output samples from the output ofthe stage-3 expander/filter 146 at the rate of 160*32F_(s), as shown byswitch 148. The resulting output y(n) is a stream of samples provided ata rate of $( \frac{147}{160} ){F_{s}.}$

[0073] Since out of 147*32=4704 samples only$( \frac{147}{160} ) \approx 1$

[0074] samples are actually provided as output samples, many samplesoutput from the stage-3 expander/filter 146 are discarded. The preferredembodiment takes advantage of this and only calculates those samplesactually provided as output samples. Some additional calculation isperformed in order to accomplish this, but since the reduction in samplecalculations is by a factor of over 4,000, this additional calculationresults in a significant reduction in memory and processingrequirements.

[0075]FIG. 7 is a block diagram of the SRC filter 140 of FIG. 6 expandedin detail to assist in understanding the selection process back throughthe stages, as explained above in connection with FIG. 5. Inimplementing the functionality of FIG. 7, FIG. 8 will also be referredto, to show how to index the SRC system such that only necessarycomputations are carried out.

[0076] Note first that if the indexing scheme were not being used, adata stream at 32*147*Fs would be seen prior to the downsampling, ordecimation, step. However, the downsampling step provided in thepreferred embodiment of the present invention takes only one out ofevery 32*160 of these samples. Referring to FIG. 8, consider the outputof stage 3 prior to downsampling to be vectors 150, 152, . . . , 154,156, of 147 samples coming at a rate of 32 Fs. This is true since thereare 147 polyphase filters in stage 3 146 (FIG. 7). To accomplish thedownsampling, it is determined which outputs, at which time steps,actually become outputs. After such determination, the method of thereferred embodiment works backwards, as it were, to find out whichsamples must be used with which filter coefficients in the variousstages to compute this output.

[0077] Table 2, below, shows which samples are used if there is a147*32*Fs Hz data stream being downsampled by 160*32. TABLE 2 OutputTime Filter 1 1 1 32*160 + 1 35 123 2*32*160 + 1 70 98 3*32*160 + 1 10573 4*32*160 + 1 140 48

[0078] This data are provided by determining which filter outputsprovide desired samples, at which time steps For example, the 4^(th)output sample is sample 3*32*160+1 prior to downsampling. This is theoutput of filter 73 at time step 105. Notice that, since the output ofstage 2 is running at 32 Fs, the output of the stage 2 that is occurringat the 105^(th) time step is exactly that 105^(th) sample.

[0079] Table 3, below, shows the general equation used to compute theoutput samples needed, the stage 2 samples that correspond to thoseoutputs, and the stage 3 filters that will be involved in computing thefinal output. TABLE 3 Output Stage 2 Sample Stage 3 Filter 1 1 132*160 + 1 35 123 2*32*160 + 1 70 98 3*32*160 + 1 105 73 4*32*160 + 1140 48 O = (i − 1)*32*160 + 1 T₁ =[O/147] F₁ = O − (T − 1)*147

[0080] Table 4, below, shows the stage 2 filters and stage 1 samplesneeded to generate the downsampled data stream. TABLE 4 Stage 2 SampleStage 1 Sample Stage 2 Filter  1 1  1  2 1  2 . . . . . . . . . 16 1 1617 2  1 . . . . . . . . . m T₂ = [m/16] F₂ = m − (T − 1)*16

[0081] The following Matlab code shows the specific case of 48 kHz to44.1 kHz conversion. The efficient indexing scheme is applied only tothe 2^(nd) and 3^(rd) stages, but could easily be extended to the 1^(st)stage as well. And, while this Matlab code shows only the case of 48 kHzto 44.1 kHz conversion, the teachings of this section can easily beextended to indexing schemes for any conversion rate.

[0082] Matlab Listing:

[0083] %Assumes 48 kHz in, 44.1 kHz out.

[0084] %1 Channel—multiple channels are just replicas

[0085] function src

[0086] %stage 1 does not implement efficient indexing

[0087] %Zero pad

[0088] ss=zeros(1, 2*max(size(in)));

[0089] ss(1:2:end)=in;

[0090] %(for “in”, start at 1, skip by two, continue to the end)

[0091] %Filter with stage 1 filter

[0092] ss=2*filter(H1_B, H1_A, ss);

[0093] %(the H1_B and H1_A vectors are read from storage)

[0094] %make polyphase filters, i.e., generate the FIR coefficients, forstage 2

[0095] %from non-polyphase stage 2 filter

[0096] for i=1:16

[0097] H2(i, :)=16*H2(i:16:end);

[0098] end

[0099] %Compuation for stages 2 and 3

[0100] for i=1:fix(147*numpts/160)−9

[0101] %subtract 9 since the first nine input samples are discarded

[0102] %to simplify initialization.

[0103] %stage 3 indicies

[0104] O=(i−1)*160*32+1;

[0105] T2=ceil(O/147);

[0106] F2=O−(T2−1)*147;

[0107] %stage 3 coefficients

[0108] %function call; go to function “A”, below

[0109] C=coef(F2);

[0110] %compute necessary stage 2 data

[0111] for j=1:3

[0112] %stage 2 indicies

[0113] m=n+j−1;

[0114] T1=ceil(m/16);

[0115] F1=m−(T1−1)*16

[0116] T1=T1+9;

[0117] %adding 9 insures that the index will not go beyond the

[0118] %file beginning, this is equivalent to discarding the

[0119] %first 9 input samples.

[0120] %perform stage 2 filters, i.e., convolve with stage 1 output

[0121] vec(j)=147*B2(F1, :)*ss(T1:−1:T1−8)′;

[0122] end

[0123] %perform stage 3 filter

[0124] in(i)=C*vec′;

[0125] end

[0126] out(1:fix(147*numpts/160)−9)=in(1:fix(147*numpts/160)−9);

[0127] %Compute Stage 3 Filter Coefficients

[0128] %function “A”:

[0129] function C=coef(m)

[0130] C=zeros(1, 3);

[0131] %calculate Eq. (6) (from text, above)

[0132] for i=1:3

[0133] n=(i−1)*147+m;

[0134] if n>=1 & n<147

[0135] C(i)=n*(n+1)/2;

[0136] elseif n>=147 & n<2*147

[0137] C(i)=147*(147+1)/2+(n−147)*(2*147−1−n);

[0138] elseif n>=2*147 & n<3*147−1

[0139] C(i)=(3*147−n−1)*(3*147−n)/2;

[0140] end

[0141] end

[0142] %prepare for convolving

[0143] C=fliplr(C)/3176523;

VI. •Σ-Δ OVERSAMPLING ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERSWITH EMBEDDED SRC FUNCTIONS

[0144] A further implementation variation will now be discussed, thatis, the use of the interpolation filter in a Σ-Δ oversampling D/Aconverter in the place of the stage-1 expander/filter 22 and the stage-2expander/filter 24 of the SRC system 20 of FIG. 2. In this way, an SRCfunction may readily be incorporated into a •Σ-Δ oversampling D/Aconverter.

[0145] Note, however, that whereas a normal SRC filter does not haveoversampled output values, a Σ-•Δ oversampling D/A converter requiresoversampled signals to feed the digital modulator. Therefore, it isimportant not to simply add a Σ-•Δ D/A interpolation filter to an SRCconstructed in accordance with the principles of the present invention,because, for example, the stage-3 expander/filter 26 of FIG. 2 may haveto generate many more output samples in such a case. Inventiveprinciples to accomplish such a combination will now be described.

[0146] First, it is advantageous to employ a modified SRC filter thatproduces an output sampled at a sample rate eight times its Nyquistsample rate. This takes advantage of a known interpolation filtertechnique in a Σ-•Δ oversampling D/A converter, that is, to upsamplesignals to an eightfold sample rate using a lowpass filter followed by asample-and-hold circuit that boosts the sample rate to a higher level,for example to 128 times the original sample rate.

[0147] Implementing such an embedded SRC filter adds considerablecomputational complexity. To reduce the computational complexity, twooptional implementations may be employed. First, note that theinterpolation filter performance in a Σ-Δ oversampling D/A converter canbe lower than that of a normal SRC filter, since high-frequency shapednoise is introduced by a digital modulator. Therefore, a filter with an80-dB stopband rejection may be employed. As a result, for a selectionof R₂=8 the performance of H₃(z) is now higher than adequate.

[0148]FIG. 9 is a diagram of a decimation filter 162 that follows a Σ−•Δmodulator 160. The modulator 160 works at a rate of F_(mod)=3.072 MHzthat is typically an oversampled rate of 64 to 384 times the firstsample rate F_(S1). A fourth-order SINC filter 164 is employed todownsample the modulator output signals to a rate of 16F_(S1). Then, asimple filter 166 such as the stage-3 expander/filter 26 of FIG. 2, withan order of N=r(S−1), is used to convert the sample rate at the SINCfilter 164 output into a rate of 16 times the final sample rate F_(S2).

[0149] This simple filter 166 performs an SRC function with a ratio ofR/(S=160). It should be pointed out that the order of the filter isbased on the decimation factor S rather than the interpolation factor R.The reason for the modification lies in the fact that there is now ananti-aliasing requirement, while such a condition is not required inother embodiments described above. In this embodiment, however, R hasbeen optimized to have only three possible values: 144, 147 or 160. Notethat when R=160 a bypass function results. The final stage 168 is a 16:1decimator.

[0150] All possible SRC cases are summarized in Table 5. From aninspection of Table 5 it is apparent that a wide range of frequentlyused audio sample rates may be converted using this approach. TABLE 5Sample Rates in A •Σ -• Δ A/D with SRC M₁ 16F_(S1) R/(S = 160) 16F_(S2)M₂ F_(S2) 4 768k 1 768k 16 48k 4 768k 147/160 705.6k 16 44.1k 6 512k 1512k 16 32k 8 384k 147/160 352.8k 16 22.05k 10 307.2k 1 307.2k 16 19.2k12 256k 1 256k 16 16k 12 256k 144/160 230.4k 16 14.4k 16 192k 147/160176.4k 16 11.025k 20 153.6k 1 153.6k 16 9.6k 24 128k 1 128k 16 8k 24128k 144/160 115.2k 16 7.2k

[0151] The design example shows that an inband SNR of over 90 dB caneasily be achieved by using the decimation/SRC filter in FIG. 9 withfour typical half-band FIR filters performing a decimation of M₂=16,just like those filters employed in normal Σ-•Δ oversampling A/Dconverters.

[0152] A compact filter procedure is now provided that implements the‘stage-3’ filter H₃(z) 166 in FIG. 9 as follows: // The ’Stage-3’ FilterCalculation Program // The SRC ratio is R/S: R is the interpolation andS the decimation ratio. // L=r(S•−1)+1 is the ’stage-3’ filter's impulseresponse length. // M=Floor(L/R) is the maximum number of termscalculated for each output. // INPUT is an array of delayed inputvalues. // INPUT[0] is the most recent input. // The RESAMPLER_INDEXregister keeps track of when an output may be // calculated as well asproviding the convolutional offset between the // input sequence and thefilter impulse response. Filter coefficients can be // evaluated basedon (5) or (6) with R₃ being replaced by S=160. 1) InitializationRESAMPLER_INDEX = R; INPUT[all] = 0; 2) do forever { wait for new input;RESAMPLER_INDEX = RESAMPLER_INDEX-R; while RESAMPLER_INDEX < R do { SUM= 0; COEFFICIENT_INDEX = RESAMPLER_INDEX + 1; for DATA_INDEX = 0 to M•−1do { SUM = SUM + INPUT[DATA_INDEX] FILT(COEFFICIENT_INDEX);COEFFICIENT_INDEX = COEFFICIENT_INDEX + R; if COEFFICIENT_INDEX > L thenexit the inner loop; } y(n) = SUM; // y(n) is the output RESAMPLER_INDEX= RESAMPLER_INDEX + S; } }

[0153] Although the present invention and its advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

What is claimed is:
 1. A method for providing a sample-rate conversion(“SRC”) filter on an input stream of sampled data provided at a firstrate, to produce an output stream of data at a second rate differentfrom said first rate, comprising the steps of: operating on said inputstream of sampled data with a first low-order interpolation filterroutine to produce a first stream of intermediate data; operating onsaid first stream of intermediate data with a first simplifiedinterpolation filter routine, having a substantially small number ofoperations to calculate the coefficients thereof, to produce a secondstream of intermediate data; and operating on said second stream ofintermediate data with a first decimating filter routine to produce saidoutput stream of data.
 2. A method as in claim 1, further comprising thestep of operating on said first stream of intermediate data with asecond low-order interpolation filter routine to produce a third streamof intermediate data; and wherein said step of operating on said firststream of intermediate data with a first simplified interpolation filterroutine is performed by operating on said third stream, rather than saidfirst stream of intermediate data.
 3. A method as in claim 1, furthercomprising the step of applying an optimizing indexing procedure inperforming instructions of said routines so as to not executeinstructions that do not generate intermediate data on which said outputstream of data is based.
 4. A method as in claim 2, wherein said step ofoperating with said first low-order interpolation filter routine isperformed by interpolating with an FIR digital interpolation filterhaving an order of between 100 and 800, and that provides said firststream of intermediate data at a rate R₁ times said first rate, where R₁is an integer less than six.
 5. A method as in claim 2, wherein saidstep of operating with said second low-order interpolation filterroutine is performed by interpolating with an FIR digital interpolationfilter having an order of between 100 and 1200, and that provides saidsecond stream of intermediate data at a rate R₂ times said first rate,where R₂ is an integer between ten and thirty-six.
 6. A method as inclaim 1, wherein said step of operating with said first simplifiedinterpolation filter routine is performed by interpolating with acascaded FIR digital interpolation filter having r filters in cascaderelation, where r is an integer between 1 and 5, having coefficientsthat are all ones, having an order of R₃−1, and that provides saidsecond stream of intermediate data at a rate R₃ times said first rate,where R₃ is an integer between 100 and 10,000.
 7. A method as in claim2, wherein said step of operating with said first simplifiedinterpolation filter routine is performed by interpolating with acascaded FIR digital interpolation filter having r filters in cascaderelation, where r is an integer between 1 and 5, having coefficientsthat are all ones, having an order of R₃−1, and that provides saidsecond stream of intermediate data at a rate R₃ times said first rate,where R₃ is an integer between 100 and 10,000.
 8. A method as in claim6, wherein said step of operating with said first simplifiedinterpolation filter routine is performed by applying said second streamof intermediate data to a digital FIR filter according to the transferfunction${H_{3}(z)} = {( {\sum\limits_{k = 0}^{R_{3} - 1}z^{- k}} )^{r}.}$


9. A method as in claim 7, wherein said step of operating with saidfirst simplified interpolation filter routine is performed by applyingsaid second stream of intermediate data to a digital FIR filteraccording to the transfer function${H_{3}(z)} = {( {\sum\limits_{k = 0}^{R_{3} - 1}z^{- k}} )^{r}.}$


10. A method for providing a sample-rate conversion (“SRC”) filter on aninput stream of sampled data provided at a first rate, to produce anoutput stream of data at a final rate that is R/S times said first rate,comprising the steps of: operating on said input stream of sampled datawith a Σ-Δ modulator filter routine to produce a first stream ofintermediate data at an oversampled rate of between 64 and 384 timessaid first rate; operating on said first stream of intermediate datawith a SINC filter routine having a fourth order to produce a secondstream of intermediate data downsampled to a rate of sixteen times saidfirst rate; operating on said second stream of intermediate data with asimplified interpolation filter routine, having a substantially smallnumber of operations to calculate the coefficients thereof, by applyinga cascaded FIR digital interpolation filter having r filters in cascaderelation, where r is an integer between 1 and 5, having coefficientsthat are all ones, having an order of r(S−1), and that provides a thirdstream of intermediate data at a rate 16 times said final rate;operating on said third stream of intermediate data with a decimatingfilter routine to produce said output stream of data.
 11. A method as inclaim 7, further comprising the step of applying an optimizing indexingprocedure in performing instructions of said routines so as to notexecute instructions that do not generate intermediate data on whichsaid output stream of data is based.
 12. A sample-rate conversion(“SRC”) filter receiving an SRC input and outputting an SRC output,comprising: a first, low-order interpolation filter receiving said SRCinput; a second, interpolation filter receiving the output of said firstfilter, and having a substantially higher order than said first filter,and having a substantially small number of operations to calculate thecoefficients thereof; a third, decimating filter receiving the output ofsaid second filter.
 13. A sample-rate conversion (“SRC”) filter as inclaim 12, further comprising a fourth, low-order interpolation filterdisposed intermediate said first filter and said second filter,receiving the output of said first filter, wherein said second filterreceives the output of said fourth filter, rather than the output ofsaid first filter.
 14. A sample-rate conversion (“SRC”) filter as inclaim 12, further comprising means for automatically determining asubset of operations required to determine said SRC filter output, andfor causing only said subset to be performed, such that the computationsinvolved in implementing said filters are reduced in number.
 15. Asample-rate conversion (“SRC”) filter receiving an SRC input andoutputting an SRC output, comprising: a first, low-order interpolationfilter receiving said SRC input; a second, low-order interpolationfilter receiving the output of said first interpolation filter, saidfirst interpolation filter and said second interpolation filter beingcascaded; a third, interpolation filter receiving the output of saidsecond interpolation filter, and having a substantially higher orderthan said first interpolation filter and said second interpolationfilter, and having a substantially small number of operations tocalculate the coefficients thereof, a first decimating filter receivingthe output of said third interpolation filter; wherein an optimizedindexing procedure that automatically determines a subset of operationsrequired to determine said SRC filter output is used to reducecomputations involved in implementing said filters.
 16. A sample-rateconversion (“SRC”) filter as in claim 15, wherein said thirdinterpolation filter includes no normalization factor.